Loads such as motors, lamps, and heaters mounted on a vehicle are powered by a battery mounted on the vehicle, to be driven. The loads are connected to the battery through semiconductor switches, and the semiconductor switches are turned on/off, thereby switching over drive/stop of the loads.
In a load circuit having a semiconductor switch and a load, a layer short in which an overcurrent is produced by a cause such as an overload, or a dead short in which an output terminal of the battery is directly short-circuited with the ground is sometimes produced. In order to protect the load circuit when such a trouble occurs, an overcurrent protection apparatus is mounted on a conventional load drive apparatus (for example, see Patent Reference 1).
FIG. 5 is a circuit diagram showing the configuration of a load drive apparatus on which a conventional overcurrent protection apparatus is mounted. As shown in the figure, the load drive apparatus has load circuits 100, 100a of plural systems (in the figure, two systems), and a battery 101 (an output voltage VB) is connected to the load circuits 100, 100a. 
The load circuit 100 is configured by a series circuit of a semiconductor switch T101 formed by, for example, a MOS-FET, and a load 102. A drive circuit 103 is connected to the gate of the semiconductor switch T101, and the gate is grounded to the ground through a semiconductor switch T102. An AND circuit AND101, a switch SW101, and a resistor R101 are connected to the input side of the drive circuit 103.
The apparatus includes a voltage detection circuit 104 which detects the both-end voltage of the semiconductor switch T101, and which compares the both-end voltage with a predetermined reference voltage. A noise removing filter 107 is disposed on the output side of the voltage detection circuit 104. The apparatus further includes a counter-electromotive force detection circuit 106 which detects a counter electromotive force E1 appearing in a power supply line 105 connecting a point P1 (a voltage V1) to which the load circuits 100, 100a are connected, with the battery 101. The apparatus further includes an AND circuit AND102, an OR circuit OR101, and a latch DF101. The resistance of the power supply line 105 is indicated by Rw1, and the inductance by L1.
Hereinafter, the operation of the load drive circuit shown in FIG. 5 will be described. In a usual state, the semiconductor switch T101 is turned on or off by a drive signal output from the drive circuit 103, to switch over drive/stop of the load 102. In the case where the current flowing through the load 102 is caused to become an overcurrent for any reason and the current increase gradient is gentle during the overcurrent, i.e., in the case where a wiring short such as a layer short occurs, the load current ID is increased. Then, the both-end voltage of the semiconductor switch T101 is raised, and the voltage detection circuit 104 outputs an overcurrent detection signal. The overcurrent detection signal is supplied to the latch DF101 through the OR circuit OR101 to turn on the semiconductor switch T102. Then, the semiconductor switch T101 is turned off to interrupt the load circuit 100, whereby the circuit can be protected.
By contrast, in the case where an accident such as that the wire connecting the semiconductor switch T101 with the load 102 is directly connected to the ground, i.e., a dead short occurs, an excessive current in which the current increase gradient is steep flows through the power supply line 105, and a large counter electromotive force E1 is generated in the power supply line 105. Then the generation of the counter electromotive force E1 is detected by the counter-electromotive force detection circuit 106, and a counter-electromotive force detection signal is output.
The counter-electromotive force detection signal is supplied to one input terminal of the AND circuit AND102, the overcurrent detection signal output from the voltage detection circuit 104 is supplied to the other input terminal, and hence an output signal of the AND circuit AND102 is at the H level. Therefore, an output signal of the OR circuit OR101 is at the H level, and hence the output of the latch DF101 is inverted, so that the semiconductor switch T102 is turned on, the semiconductor switch T101 is turned off, and the load circuit 100 is interrupted.
The reason why the AND circuit AND102 is disposed is that the load circuit (the load circuit 100a) other than the load circuit 100 in which the dead short occurs is not caused to be interrupted. In a configuration where the AND circuit AND102 is not disposed, when a dead short occurs in one of the plural load circuits 100, 100a, all of the load circuits connected to the battery 101 are interrupted. In order to prevent this phenomenon from occurring, the AND circuit AND102 is disposed.
However, the overcurrent protection apparatus having the above-described configuration uses the output of the logical sum (AND) of the overcurrent detection signal output from the voltage detection circuit 104, and the counter-electromotive force detection signal output from the counter-electromotive force detection circuit 106. Therefore, the operation of the latch DF101 is depend on the overcurrent detection signal output from the voltage detection circuit 104, and, when generation of a counter electromotive force is detected, the load circuit 100 cannot be instantly interrupted.
Patent Reference 1: JP-A-2006-5581